FAN9612MX【PDF 20/36 页】IC CTLR PFC DUAL BCM 16SOICN

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Sheet目录38

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?2008 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN9612 " Rev. 1.1.7

6. Disabling the FAN9612

There are four ways to disable the FAN9612. It is

important to understand how the part reacts for the

various shutdown procedures.

a. Pull the SS Pin to GND

. This method uses the error

amplifier to stop the operation of the power supply.

By pulling the SS pin to GND, the error amplifiers

non-inverting input is pulled to GND. The amplifier

senses that the inverting input (FB pin) is higher

than the reference voltage and tries to adjust its

output (COMP pin) to make the FB pin equal to the

reference at the SS pin. Due to the slow speed of

the voltage loop in PFC applications, this might take

several line cycles. Thus, it is important to consider

that by pulling the SS pin to GND, the power supply

is not shut down immediately. Recovery from a shut

down follows normal soft-start procedure when the

SS pin is released.

b. Pull the FB Pin to GND

. By pulling the FB pin below

the open feedback protection threshold of

approximately 0.5 V, the power supply can be shut

down immediately. It is imperative that the FB is

pulled below the threshold very quickly since the

power supply keeps switching until this threshold is

crossed. If the feedback is pulled LOW softly and

does not cross the threshold, the power supply tries

to deliver maximum power because the FB pin is

forced below the reference voltage of the error

amplifier on the SS pin. Eventually, as FB is pulled

to GND, the SS capacitor is pulled LOW by the

internal clamp between the FB and SS pins. The

SS pin stays approximately 0.5 V higher than the

FB pin itself. Therefore, recovery from a shut down

state follows normal soft-start procedure when the

FB pin is released as the voltage across the SS

capacitor starts ramping from a low value.

c. Pulling the COMP Pin to GND

. When the COMP

pin is pulled below the PWM ramp offset,

approximately 0.195 V, the FAN9612 stops sending

gate drive pulses to the power MOSFETs. This

condition is similar to pulse skipping under no-load

condition. If any load is still present at the output of

the boost PFC stage, the output voltage decreases.

Consequently, the FB pin decreases and the SS

capacitor voltage is pulled LOW by the internal

clamp between the FB and SS pins. At that point,

the operation and eventual recovery to normal

operation is similar to the mechanism described

above. If the COMP pin is held LOW for long

enough to pull the SS pin LOW, the recovery

follows normal soft-start procedure when the COMP

pin is released. If the SS capacitor is not pulled

LOW as a result of a momentary pull-down of the

COMP pin, the recovery is still soft due to the fact

that a limited current source is charging the

compensation capacitors at the output of the error

amplifier. Nevertheless, in this case, output voltage

overshoot can occur before the voltage loop enters

closed-loop operation and resumes controlling the

output voltage again.

d. Pull the VIN Pin to GND

. Since the VIN sense

circuit is configured to ride through a single line

cycle dropout test without shutting down the power

supply, this method results in a delayed shutdown

of the converter. The FAN9612 stops operation

approximately 20 ms to 32 ms after the VIN pin is

pulled LOW. The delay depends on the phase of

the line cycle at which the pull-down occurs. This

method triggers the input brownout protection (input

under-voltage lockout), which gradually discharges

the compensation capacitor. As the output voltage

decreases, the FB pin falls, pulling LOW the SS

capacitor voltage. Similarly to the shutdown, once

the VIN pin is released, operation resumes after

several milliseconds of delay needed to determine

that the input voltage is above the turn-on

threshold. At least one line cycle peak must be

detected above the turn-on threshold before

operation can resume at the following line voltage

zero-crossing. The converter starts following normal

soft-start procedure.

7. Layout and Connection Guidelines

For high-power applications, two or more PCB layers

are recommended to effectively use the ground pattern

to minimize the switching noise interference.

The FAN9612 incorporates fast-reacting input circuits,

short propagation delays, and strong output stages

capable of delivering current peaks over 1.5 A to

facilitate fast voltage transition times. Many high-speed

power circuits can be susceptible to noise injected from

their own output or external sources, possibly causing

output re-triggering. These effects can be especially

obvious if the circuit is tested in breadboard or non-

optimal circuit layouts with long input or output leads.

The following guidelines are recommended for all layout

designs, but especially strongly for the single-layer PCB

designs. (For example of a 1-layer PCB design, see the

Application Note AN-6086.)

General

? Keep high-current output and power ground paths

separate from analog input signals and signal

ground paths.

? For best results, make connections to all pins as

short and direct as possible.

Power Ground and Analog Ground

? Power ground (PGND) and analog ground (AGND)

should meet at one point only.

? All the control components should be connected to

AGND without sharing the trace with PGND.

? The return path for the gate drive current and V

capacitor should be connected to the PGND pin.

? Minimize the ground loops between the driver

outputs (DRV1, DRV2), MOSFETs, and PGND.

? Adding the by-pass capacitor for noise on the VDD

pin is recommended. It should be connected as

close to the pin as possible.

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